1. Field of the Invention
The disclosures herein generally relate to a nonvolatile memory cell, and particularly relate to a nonvolatile memory cell which is capable of retaining stored data in the absence of a power supply voltage.
2. Description of the Related Art
Nonvolatile semiconductor memory devices, which can retain stored data even in the absence of supplied power, conventionally include flash EEPROM employing a floating gate structure, FeRAM employing a ferroelectric film, MRAMs employing a ferromagnetic film, etc. There is a new type of nonvolatile semiconductor memory device called PermSRAM. PermSRAM uses a MIS (metal-insulating film-semiconductor) transistor as a nonvolatile memory cell. This nonvolatile memory cell has the same structure as an ordinary MIS transistor, and thus requires no special structure such as a floating gate or a special material such as a special material offers an advantage in cost ferroelectric material or ferromagnetic material. The absence of either a special structure or a reduction. PermSRAM was initially disclosed in PCT/JP2003/016143, which was filed on Dec. 17, 2003, the entire contents of which are hereby incorporated by reference.
A MIS transistor serving as a nonvolatile memory cell in PermSRAM is configured to experience a hot-carrier effect on purpose for storage of one-bit data. The hot-carrier effect refers to the injection of electrons into the gate insulating film and/or sidewall of a MIS transistor. This causes a nonvolatile change in the transistor characteristics, which may be a rise in the threshold voltage, i.e., an increase in the channel resistance. A change in the transistor characteristics caused by the hot-carrier effect may be utilized to represent one-bit data “0” or “1”. Detecting the stored data may involve the use of a pair of MIS transistors, one of which is designed to experience the hot-carrier effect. A difference in the ON current between the two paired MIS transistors may be detected by using a sense circuit such as a one-bit static memory circuit (i.e., latch) coupled to the pair of MIS transistors.
A hot-carrier effect is asymmetric with respect to the positions of the source and drain of a transistor. When the source node and drain node used to apply a bias for generating a hot-carrier effect are used as a source node and a drain node, respectively, at the time of detecting a drain current, the detected drain current exhibits a relatively small drop caused by the hot-carrier effect. When the source node and drain node used to apply a bias for generating a hot-carrier effect are swapped and used as a drain node and a source node, respectively, at the time of detecting a drain current, the detected drain current exhibits a significant drop caused by the hot-carrier effect. The difference in the detected drain current between these two scenarios is approximately a factor of 10.
Such asymmetric characteristics of a hot-carrier effect are attributable to the fact that most of the electrons injected by the hot-carrier effect into the gate insulating film and/or sidewall are situated closer to the drain node than to the source node. Specifically, the MIS transistor operating in the saturation region has the channel thereof pinched off and closed by a depletion layer near the drain. As a result, the strongest electric field in the horizontal direction occurs in this depletion layer in the proximity of the drain. Some of the electrons accelerated by this strong electric field and thus having high energy are injected into the gate insulating film and/or sidewall in the proximity of the drain.
It may be noted that the gate insulating film and/or sidewall serve as a charge trapping layer. For the purpose of keeping the injected electrons trapped in the charge trapping layer, the use of the sidewall for the trapping purposes may be more preferable than the use of the gate insulating film. This is because the sidewall may be thicker than the gate insulating film, and may also be more easily designed to have a potential well structure for the trapping purposes.
In order to inject electrons into the sidewall on the drain side by applying a bias for generating the hot-carrier effect, it is desirable to ensure the presence of a depletion layer situated directly below the drain-side sidewall. This is because the strongest electrical field in the horizontal direction emerges in such a depletion layer as described above. Since the impurity diffusion regions (i.e. impurity diffusion layers) are formed by utilizing the gate electrode and sidewalls as a mask, the end of an impurity diffusion region tends to be aligned with the end of a sidewall. This ensures the presence of a depletion layer situated directly below the drain-side sidewall.
With advancement in the miniaturization of semiconductor devices, however, it has become more and more difficult to align the end of an impurity diffusion region with the end of a sidewall. Diffusion of ions at the time of doping and at the time of heat treatment causes the impurity diffusion region to spread spatially in the horizontal directions. This results in the end of the impurity diffusion region intruding into areas situated directly below the sidewall.
The provision of a sidewall having substantially wide width may still secure the presence of a depletion layer despite the horizontal spreading of an impurity diffusion region. The miniaturization of semiconductor devices, however, causes the width of sidewalls to become narrower and narrower, resulting in the end of the impurity diffusion region intruding into the area directly below the gate electrode. When this happens, no depletion layer may be present in the area situated directly below the sidewall even when a bias voltage creates a depletion layer inside the impurity diffusion region in the proximity of the end thereof. In such a case, a depletion layer is in existence under the gate electrode, but is not in existence under the sidewall because of the horizontal spreading of the impurity diffusion region. Consequently, the generation of hot carriers does not occur directly below the drain-side sidewall, thereby failing to enable sufficient injection of hot carriers into the sidewall serving as a charge trapping layer.